Research Journal of Applied Sciences, Engineering and Technology
By utilizing a CAN (Controller Area Network) bus, point to point wiring is substituted by a share... more By utilizing a CAN (Controller Area Network) bus, point to point wiring is substituted by a shared medium. This is done by adding hardware (embedded systems) to each control unit that uses CAN protocol. The main purpose of this study is communication software protocol design and implementation based on CAN protocol (on CAN) for intra-communication in a micro satellite that can be used for intra-communication of other embedded systems. This protocol is designed in the application layer and is conformed to MAC and PHY layers of CAN protocol.
This paper presents a new method to implement a multiplier using the Quasi Delay Insensitive (QDI... more This paper presents a new method to implement a multiplier using the Quasi Delay Insensitive (QDI) approach. QDI circuits allow unbounded delays on wires and gates, and require the difference among the delays in forks to be less than the delays of their terminating gates. To implement the Booth multiplier following the QDI approach, we considered Martin's method. In this method, an asynchronous circuit is considered as a set of cells that communicate through a handshaking protocol, and is synthesized from a high level definition through different levels of translation. The main problem related to the resulting circuits their considerable overhead due to the implementation of handshaking protocols. In our proposed method, the overhead is reduced 50% by separating the control and data path units. This solution increases the forks, and causes complexity in physical implementation. By applying some of the rules derived from Martin's method, the forks became locally limited to ease up the physical implementation.
Many of digital transmission and storage systems use Forward Error Correction (FEC) techniques fo... more Many of digital transmission and storage systems use Forward Error Correction (FEC) techniques for correcting errors occurring during the transmission, storage, or retrieval of data. Viterbi Algorithm [480,2] belongs to a large class of FEC known as convolution codes which are used in a wide range of applications such as wireless communications, digital mobile telephony, digital TV broadcast, CD-ROMs, and magnetic disks. The basic idea behind the Viterbi decoder is to maximize the correlation between received vector and the table of possible codewords while sequentially performing the opposite operation of the encoder. The Viterbi decoder operates by finding the maximum likelihood of the decoding sequence. The quality of a Viterbi decoder design is mainly measured by three criteria: coding gain, throughput, and power dissipation [3]. High coding gain results in low data transfer error probability while high throughput is necessary for high-speed applications. The design of Viterbi decoders with high coding gain and throughput is made challenging by the need for a low power circuit implementation. This requirement mainly stems from the fact that the Viterbi decoders are often placed in communication systems running on batteries where the power reduction is a must. Several attempts for reducing the power dissipation in the Viterbi decoder have been
ABSTRACT Coverage and tracking of multiple targets, are viewed as important challenges in WSNs, m... more ABSTRACT Coverage and tracking of multiple targets, are viewed as important challenges in WSNs, mainly aimed for future ubiquitous and pervasive applications. Target coverage in WSNs with large numbers of sensor nodes and targets, and with a predefined placement of sensors, may be conducted through adjusting the sensing range and considering the energy consumption related to this operation. In this paper, we encounter the problem of multiple target coverage in WSNs by determining the sensing range of each sensor node to maximize the total utility of the network. We solve this Network Utility Maximization (NUM) problem via two approaches, primal and dual decompositions, which result in iterative distributed price-based algorithms. Convergence of sensing ranges to optimal values is proved by means of stability analysis and simulation experiments. Simulation results show convergence to optimal values in few iterations, with near optimal values for the total objective function and energy consumption of nodes. These results show scalability of our algorithm, in terms of the number of iterations needed for convergence when compared with the other two methods. Furthermore, the distributed algorithm based on dual decomposition is used to cover efficiently moving targets in consecutive time intervals.
This study presents Intra-Inter Block Control Flow Checking method (I2BCFC) based on software ins... more This study presents Intra-Inter Block Control Flow Checking method (I2BCFC) based on software instruction level redundancy for intra-inter block control flow errors detection. In utilizing electronic equipment, space applications designers have two options ahead: radiation-hardening or radiation-tolerant equipment and Commercial Off-The Shelf (COTS) equipment which COTS is the appropriate option due to some reasons like cost and accessibility in many applications. COTS equipment in applications like space missions do not have tolerance capability against some threats such as Single Event Upsets (SEU). Therefore, there should be considerations in resisting these equipment against possible threats. I2BCFC as a technique for COTS reliability increase, has the overhead of 29% in memory in relation to the without code redundancy and this rate has at least 11% improvement in memory overhead in comparison with the previous methods. I2BCFC method has the average performance overheard of 27% in comparison with the normal state of program that it is 5% better than the previous methods.
Ieee Transactions on Industrial Informatics, Feb 1, 2014
Mechatronic systems operating in industrial environments are subject to a variety of threats beca... more Mechatronic systems operating in industrial environments are subject to a variety of threats because of harsh conditions. Industrial systems usually use commercial off-the shelf (COTS) equipment which are not robust and safe against hostile conditions and therefore require fault-tolerance considerations. This paper presents a novel and efficient method for online detection of control flow errors, called software-based control flow checking (SCFC). It is implemented purely in software and does not manipulate the hardware architecture of the system. Redundant instructions and signatures are embedded into the program at compile time and are utilized for control flow checking at run time. The signatures of the basic blocks are derived from the program graph. It is shown in the paper that SCFC method can increase single detection capability to 14.7% and the fault coverage to 6.12% averagely in comparison with other methods without any increase in memory and performance overheads. In the paper, besides experimental evaluations, analytical evaluations are also carried out, based on probability principles. The detection ability of each method used is thus computed. These computations verify the experimental results and show that SCFC can detect more errors than other methods suggested in literature. Considering the memory limitations in some (such as space) applications and the trend towards the requirement for faster execution of programs, we suggest a novel metric called fitness parameter which incorporates these. It is a better measure than the previously proposed ones since it considers the fault coverage, the memory overhead and the execution time (performance overhead) of each method simultaneously, as well as the detection capability.
In this paper we will show that it is both possible and easy to use a standard HDL language like ... more In this paper we will show that it is both possible and easy to use a standard HDL language like Verilog HDL, along with PLI to model asynchronous circuits at all levels of abstraction, including the behavioral level (CSP level). Our method allows CSP (Communicating Sequential ...
Difficulties of synchronous circuits such as clock skew, power consumption, worst-case delay, and... more Difficulties of synchronous circuits such as clock skew, power consumption, worst-case delay, and physical sensitivity pave way for asynchronous designs. There are different asynchronous delay models; among them Delay Insensitive (DI) is one of the most popular models. A ...
Complexity of design and testing are the major obstacle for widespread use of asynchronous circui... more Complexity of design and testing are the major obstacle for widespread use of asynchronous circuit in digital circuit design. Template based synthesis of asynchronous circuit is accepted as an effective way to decrease complexity of design of asynchronous circuit. One of the popular pre-designed templates that most synthesis tools use it to synthesis QDI asynchronous circuit is Pre-Charged Full Buffers (PCFB). In this paper we study the effect of single stuck-at fault in PCFB templates and categorize fault effects, then for each category introduce a circuit that detect faults. Experimental results show that using these additional circuits in PCFB buffers can improve the testability from 68.55 percent to 90.32 percent.
Proceedings of the 2005 Acm Sigda 13th International Symposium on Field Programmable Gate Arrays, 2005
This paper introduces a methodology for prototyping Globally Asynchronous Locally Synchronous (GA... more This paper introduces a methodology for prototyping Globally Asynchronous Locally Synchronous (GALS) circuits on synchronous commercial FPGAs. A library of required elements for implementing GALS circuits is proposed and general design considerations to successfully implement a GALS circuit on FPGA are discussed. The library includes clock generators and arbiters, and different port controllers. Different implementations of these circuits and their advantages and disadvantages are explored. At the end we present a GALS Reed-Solomon decoder as a practical example. The results show that the GALS approach improves the performance of the circuit by 11% and reduces the power consumption by 18.7% to 19.6% considering different error rates. On the other hand, the area of the circuit is increased by 51% which is acceptable considering that a pure synchronous circuit including a central controller is decomposed to generate GALS system and 29% of this overhead belongs to distributing controller in different modules. Deploying better decomposition methods can reduce this overhead substantially.
ABSTRACT In this paper we propose a method to generate pausible clock based GALS wrapper circuits... more ABSTRACT In this paper we propose a method to generate pausible clock based GALS wrapper circuits from the synchronous module's Verilog specification code automatically. We first parse the input module specification and produce wrapper circuit components based on the ...
Abstract. Current technology trends have led to the growing impact of process variations on perfo... more Abstract. Current technology trends have led to the growing impact of process variations on performance of asynchronous circuits. As it is impera-tive to model process parameter variations for sub-100nm technologies to produce a more real performance metric, it is equally important to ...
2007 6th IEEE Dallas Circuits and Systems Workshop on System-on-Chip, 2007
Scaling the technology and reducing the feature size in integrated circuits have caused leakage p... more Scaling the technology and reducing the feature size in integrated circuits have caused leakage power consumption to become one of the main challenges to the digital design. Dual-threshold CMOS circuit, which has both high and low threshold transistors in a single chip, can be used to deal with the leakage problem in high performance applications. This paper presents dual-threshold voltage technique for reducing leakage power dissipation of Pre-Charge Full Buffer asynchronous linear-pipelines while still maintaining high performance. We employed Folded Dependency Graph to produce a formal performance analysis. In order to reduce leakage power an algorithm for assigning a high threshold voltage is proposed. Results obtained indicate that our proposed technique can achieve on average 30% savings for leakage power, while there is no performance penalty.
Research Journal of Applied Sciences, Engineering and Technology
By utilizing a CAN (Controller Area Network) bus, point to point wiring is substituted by a share... more By utilizing a CAN (Controller Area Network) bus, point to point wiring is substituted by a shared medium. This is done by adding hardware (embedded systems) to each control unit that uses CAN protocol. The main purpose of this study is communication software protocol design and implementation based on CAN protocol (on CAN) for intra-communication in a micro satellite that can be used for intra-communication of other embedded systems. This protocol is designed in the application layer and is conformed to MAC and PHY layers of CAN protocol.
This paper presents a new method to implement a multiplier using the Quasi Delay Insensitive (QDI... more This paper presents a new method to implement a multiplier using the Quasi Delay Insensitive (QDI) approach. QDI circuits allow unbounded delays on wires and gates, and require the difference among the delays in forks to be less than the delays of their terminating gates. To implement the Booth multiplier following the QDI approach, we considered Martin's method. In this method, an asynchronous circuit is considered as a set of cells that communicate through a handshaking protocol, and is synthesized from a high level definition through different levels of translation. The main problem related to the resulting circuits their considerable overhead due to the implementation of handshaking protocols. In our proposed method, the overhead is reduced 50% by separating the control and data path units. This solution increases the forks, and causes complexity in physical implementation. By applying some of the rules derived from Martin's method, the forks became locally limited to ease up the physical implementation.
Many of digital transmission and storage systems use Forward Error Correction (FEC) techniques fo... more Many of digital transmission and storage systems use Forward Error Correction (FEC) techniques for correcting errors occurring during the transmission, storage, or retrieval of data. Viterbi Algorithm [480,2] belongs to a large class of FEC known as convolution codes which are used in a wide range of applications such as wireless communications, digital mobile telephony, digital TV broadcast, CD-ROMs, and magnetic disks. The basic idea behind the Viterbi decoder is to maximize the correlation between received vector and the table of possible codewords while sequentially performing the opposite operation of the encoder. The Viterbi decoder operates by finding the maximum likelihood of the decoding sequence. The quality of a Viterbi decoder design is mainly measured by three criteria: coding gain, throughput, and power dissipation [3]. High coding gain results in low data transfer error probability while high throughput is necessary for high-speed applications. The design of Viterbi decoders with high coding gain and throughput is made challenging by the need for a low power circuit implementation. This requirement mainly stems from the fact that the Viterbi decoders are often placed in communication systems running on batteries where the power reduction is a must. Several attempts for reducing the power dissipation in the Viterbi decoder have been
ABSTRACT Coverage and tracking of multiple targets, are viewed as important challenges in WSNs, m... more ABSTRACT Coverage and tracking of multiple targets, are viewed as important challenges in WSNs, mainly aimed for future ubiquitous and pervasive applications. Target coverage in WSNs with large numbers of sensor nodes and targets, and with a predefined placement of sensors, may be conducted through adjusting the sensing range and considering the energy consumption related to this operation. In this paper, we encounter the problem of multiple target coverage in WSNs by determining the sensing range of each sensor node to maximize the total utility of the network. We solve this Network Utility Maximization (NUM) problem via two approaches, primal and dual decompositions, which result in iterative distributed price-based algorithms. Convergence of sensing ranges to optimal values is proved by means of stability analysis and simulation experiments. Simulation results show convergence to optimal values in few iterations, with near optimal values for the total objective function and energy consumption of nodes. These results show scalability of our algorithm, in terms of the number of iterations needed for convergence when compared with the other two methods. Furthermore, the distributed algorithm based on dual decomposition is used to cover efficiently moving targets in consecutive time intervals.
This study presents Intra-Inter Block Control Flow Checking method (I2BCFC) based on software ins... more This study presents Intra-Inter Block Control Flow Checking method (I2BCFC) based on software instruction level redundancy for intra-inter block control flow errors detection. In utilizing electronic equipment, space applications designers have two options ahead: radiation-hardening or radiation-tolerant equipment and Commercial Off-The Shelf (COTS) equipment which COTS is the appropriate option due to some reasons like cost and accessibility in many applications. COTS equipment in applications like space missions do not have tolerance capability against some threats such as Single Event Upsets (SEU). Therefore, there should be considerations in resisting these equipment against possible threats. I2BCFC as a technique for COTS reliability increase, has the overhead of 29% in memory in relation to the without code redundancy and this rate has at least 11% improvement in memory overhead in comparison with the previous methods. I2BCFC method has the average performance overheard of 27% in comparison with the normal state of program that it is 5% better than the previous methods.
Ieee Transactions on Industrial Informatics, Feb 1, 2014
Mechatronic systems operating in industrial environments are subject to a variety of threats beca... more Mechatronic systems operating in industrial environments are subject to a variety of threats because of harsh conditions. Industrial systems usually use commercial off-the shelf (COTS) equipment which are not robust and safe against hostile conditions and therefore require fault-tolerance considerations. This paper presents a novel and efficient method for online detection of control flow errors, called software-based control flow checking (SCFC). It is implemented purely in software and does not manipulate the hardware architecture of the system. Redundant instructions and signatures are embedded into the program at compile time and are utilized for control flow checking at run time. The signatures of the basic blocks are derived from the program graph. It is shown in the paper that SCFC method can increase single detection capability to 14.7% and the fault coverage to 6.12% averagely in comparison with other methods without any increase in memory and performance overheads. In the paper, besides experimental evaluations, analytical evaluations are also carried out, based on probability principles. The detection ability of each method used is thus computed. These computations verify the experimental results and show that SCFC can detect more errors than other methods suggested in literature. Considering the memory limitations in some (such as space) applications and the trend towards the requirement for faster execution of programs, we suggest a novel metric called fitness parameter which incorporates these. It is a better measure than the previously proposed ones since it considers the fault coverage, the memory overhead and the execution time (performance overhead) of each method simultaneously, as well as the detection capability.
In this paper we will show that it is both possible and easy to use a standard HDL language like ... more In this paper we will show that it is both possible and easy to use a standard HDL language like Verilog HDL, along with PLI to model asynchronous circuits at all levels of abstraction, including the behavioral level (CSP level). Our method allows CSP (Communicating Sequential ...
Difficulties of synchronous circuits such as clock skew, power consumption, worst-case delay, and... more Difficulties of synchronous circuits such as clock skew, power consumption, worst-case delay, and physical sensitivity pave way for asynchronous designs. There are different asynchronous delay models; among them Delay Insensitive (DI) is one of the most popular models. A ...
Complexity of design and testing are the major obstacle for widespread use of asynchronous circui... more Complexity of design and testing are the major obstacle for widespread use of asynchronous circuit in digital circuit design. Template based synthesis of asynchronous circuit is accepted as an effective way to decrease complexity of design of asynchronous circuit. One of the popular pre-designed templates that most synthesis tools use it to synthesis QDI asynchronous circuit is Pre-Charged Full Buffers (PCFB). In this paper we study the effect of single stuck-at fault in PCFB templates and categorize fault effects, then for each category introduce a circuit that detect faults. Experimental results show that using these additional circuits in PCFB buffers can improve the testability from 68.55 percent to 90.32 percent.
Proceedings of the 2005 Acm Sigda 13th International Symposium on Field Programmable Gate Arrays, 2005
This paper introduces a methodology for prototyping Globally Asynchronous Locally Synchronous (GA... more This paper introduces a methodology for prototyping Globally Asynchronous Locally Synchronous (GALS) circuits on synchronous commercial FPGAs. A library of required elements for implementing GALS circuits is proposed and general design considerations to successfully implement a GALS circuit on FPGA are discussed. The library includes clock generators and arbiters, and different port controllers. Different implementations of these circuits and their advantages and disadvantages are explored. At the end we present a GALS Reed-Solomon decoder as a practical example. The results show that the GALS approach improves the performance of the circuit by 11% and reduces the power consumption by 18.7% to 19.6% considering different error rates. On the other hand, the area of the circuit is increased by 51% which is acceptable considering that a pure synchronous circuit including a central controller is decomposed to generate GALS system and 29% of this overhead belongs to distributing controller in different modules. Deploying better decomposition methods can reduce this overhead substantially.
ABSTRACT In this paper we propose a method to generate pausible clock based GALS wrapper circuits... more ABSTRACT In this paper we propose a method to generate pausible clock based GALS wrapper circuits from the synchronous module's Verilog specification code automatically. We first parse the input module specification and produce wrapper circuit components based on the ...
Abstract. Current technology trends have led to the growing impact of process variations on perfo... more Abstract. Current technology trends have led to the growing impact of process variations on performance of asynchronous circuits. As it is impera-tive to model process parameter variations for sub-100nm technologies to produce a more real performance metric, it is equally important to ...
2007 6th IEEE Dallas Circuits and Systems Workshop on System-on-Chip, 2007
Scaling the technology and reducing the feature size in integrated circuits have caused leakage p... more Scaling the technology and reducing the feature size in integrated circuits have caused leakage power consumption to become one of the main challenges to the digital design. Dual-threshold CMOS circuit, which has both high and low threshold transistors in a single chip, can be used to deal with the leakage problem in high performance applications. This paper presents dual-threshold voltage technique for reducing leakage power dissipation of Pre-Charge Full Buffer asynchronous linear-pipelines while still maintaining high performance. We employed Folded Dependency Graph to produce a formal performance analysis. In order to reduce leakage power an algorithm for assigning a high threshold voltage is proposed. Results obtained indicate that our proposed technique can achieve on average 30% savings for leakage power, while there is no performance penalty.
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Papers by Hossein Pedram