Papers by Habib Muhammad Nazir Ahmad
Journal of Low Power Electronics and Applications
2012 UKSim 14th International Conference on Computer Modelling and Simulation, 2012
The main objective of this paper is to design a novel threshold voltage detector circuit using ca... more The main objective of this paper is to design a novel threshold voltage detector circuit using carbon nanotube field effect transistor (CNTFET). This circuit is simulated in HSPICE by using HSPICE model of CNTFET. The uniqueness of this proposed circuit is that the threshold voltage of each CNTFET decides each voltage detection level where as in CMOS implementation a complex band-gap reference circuit is needed to produce a reference voltage level for precise detection. MOSFETs with different threshold voltage can also be used to implement this idea but that would add a new Vth mask for each different voltage detection level which will increase the process cost significantly. Therefore this new proposed CNTFET based voltage level detection circuit can produce much improved performance with significant reduction in implementation complexity by both saving number of mask set and reducing the chip area significantly.
This paper proposes a new design technique of a stable, low input impedance, high sensitivity, h... more This paper proposes a new design technique of a stable, low input impedance, high sensitivity, high gain and low-power Potentiostat using carbon nanotube FETs (CNTFETs) at
32 nm level that utilizes different input voltages for verifying
voltage follower performance. The fully differential architecture
suppresses the common mode interference. Extensive
simulations have been performed to investigate the distribution of the power and delay of the CNTFET-based Potentiostat due to variations in the supply voltage and temperature of the CNTFETs. The CNTFET-based Potentiostat demonstrates that it tolerates the PVT (Process, Voltage, and Temperature) variations significantly better than its CMOS counterpart.
This manuscript reports and analyzes
12-CNTFET and GDI CNTFET based full adder
implementation a... more This manuscript reports and analyzes
12-CNTFET and GDI CNTFET based full adder
implementation at 32 nm level. As figures of merit, stability,
power dissipation and Power Delay Product (PDP) are
considered for the best overall performance. Intensive HSPICE
simulations have been performed to investigate the distribution
of the power and delay of the CNTFET-based full adders. Both
circuit has noticeable reduction in short current power
consumption but in terms of comparison GDI CNTFET shows
better performance in both power consumption and Power
Delay Product (PDP) variations. The CNTFET-based One bit
Full Adder cell demonstrates that it tolerates the PVT (Process,
Voltage, and Temperature) variations significantly better than
its CMOS counterpart.
On the basis of acquired knowledge, the extraction of different JFET parameters using a novel met... more On the basis of acquired knowledge, the extraction of different JFET parameters using a novel method (i.e., the Yfunction technique) in associated with the series resistance ( ܴ ௦ௗ ), drain current ܫ( ௗ௦ ) and the output conductance( ܩ ௨௧ ) is presented in this paper. The result is some general, simple and correct expressions, which has not been previously available in the literature. The technique that we used here to determine the drain current for JFET includes the MOSFET square law model [1]. This technique relies on combining drain current, the body effect coefficient ݉ and the gate oxide permittivity (߳ ை ) and gate oxide thickness ݐ( ை ), which requires reliable values of the threshold voltage (ܸ ௧ ), the MOSFET inversion layer effective electron mobility (ߤ ), mobility attenuation coefficient (ߠ), the series resistance (ܴ ௦ௗ ) to be obtained. The extracted drain current, effective mobility total resistance and output conductance values are shown through simulation. The extracted results have been shown in good agreement with simulation to demonstrate the validity of the presented analytical expressions.
Orthogonal Frequency Division Multiplexing (OFDM) using M-ary Quadrature Amplitude Modulation (QA... more Orthogonal Frequency Division Multiplexing (OFDM) using M-ary Quadrature Amplitude Modulation (QAM) is a very common approach in multicarrier communication. With the increasing demand of multimedia communication, the concept of OFDM was introduced. In this paper, we have shown a comparative analysis between the traditional binary mapped 16-QAM and gray mapped 16-QAM scheme with OFDM in both AWGN and Rayleigh fading channel. We have chosen the parameters SER vs SNR for binary mapping and BER vs SNR for Gray mapping for the performance analysis as these two are the most important parameter for any wireless communications. The selection of 16-QAM scheme was made to reduce the complexity of higher order QAM constellations which are more susceptible to noise.
This paper deals with a technique that extracts the MOSFET parameter using the Y-function techniq... more This paper deals with a technique that extracts the MOSFET parameter using the Y-function technique, in conjunction with the drain current, the transconductance data and the series resistance ( ) in silicon nanowire FET's (Si-NWFET). This technique relies on combining drain current and output conductance, which enables reliable values of the threshold voltage ( ) , mobility ( ) , mobility attenuation coefficient ( ), the series resistance ( ) to be obtained. The extracted drain current, effective mobility total resistance and output conductance values are shown through MATLAB simulation. The extracted results have been shown in good agreement with simulation which expresses the validity of our proposed technique. The technique only requires a single device for extraction of ( ) and the iteration procedure for fitting the data.
In communication circuitry detection of ultra weak signals at reception end is delicate. In order... more In communication circuitry detection of ultra weak signals at reception end is delicate. In order to have precision performance and acceptable gain in ultra wide band frequency range the noise performance and power consumption for low noise amplifier is significant. Among different techniques, this paper presents the simulated result for a distributed low noise amplifier with four stage amplification to ensure minimum noise figure as well as low power consumption. The simulation work is based on TSMC 0.18μm process parameter.
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Papers by Habib Muhammad Nazir Ahmad
32 nm level that utilizes different input voltages for verifying
voltage follower performance. The fully differential architecture
suppresses the common mode interference. Extensive
simulations have been performed to investigate the distribution of the power and delay of the CNTFET-based Potentiostat due to variations in the supply voltage and temperature of the CNTFETs. The CNTFET-based Potentiostat demonstrates that it tolerates the PVT (Process, Voltage, and Temperature) variations significantly better than its CMOS counterpart.
12-CNTFET and GDI CNTFET based full adder
implementation at 32 nm level. As figures of merit, stability,
power dissipation and Power Delay Product (PDP) are
considered for the best overall performance. Intensive HSPICE
simulations have been performed to investigate the distribution
of the power and delay of the CNTFET-based full adders. Both
circuit has noticeable reduction in short current power
consumption but in terms of comparison GDI CNTFET shows
better performance in both power consumption and Power
Delay Product (PDP) variations. The CNTFET-based One bit
Full Adder cell demonstrates that it tolerates the PVT (Process,
Voltage, and Temperature) variations significantly better than
its CMOS counterpart.
32 nm level that utilizes different input voltages for verifying
voltage follower performance. The fully differential architecture
suppresses the common mode interference. Extensive
simulations have been performed to investigate the distribution of the power and delay of the CNTFET-based Potentiostat due to variations in the supply voltage and temperature of the CNTFETs. The CNTFET-based Potentiostat demonstrates that it tolerates the PVT (Process, Voltage, and Temperature) variations significantly better than its CMOS counterpart.
12-CNTFET and GDI CNTFET based full adder
implementation at 32 nm level. As figures of merit, stability,
power dissipation and Power Delay Product (PDP) are
considered for the best overall performance. Intensive HSPICE
simulations have been performed to investigate the distribution
of the power and delay of the CNTFET-based full adders. Both
circuit has noticeable reduction in short current power
consumption but in terms of comparison GDI CNTFET shows
better performance in both power consumption and Power
Delay Product (PDP) variations. The CNTFET-based One bit
Full Adder cell demonstrates that it tolerates the PVT (Process,
Voltage, and Temperature) variations significantly better than
its CMOS counterpart.